Processing-in-Memory (PIM) Market Size & Share 2026-2035

Processing-in-Memory (PIM) Market Size

The global processing-in-memory (PIM) market is valued at USD 611.5 million in 2025 and is projected to reach USD 850 million in 2026 and USD 8.5 billion by 2035, expanding at a CAGR of 29.2% during 2026–2035.

The forecast reflects a shift in AI infrastructure economics: moving model weights and intermediate data between processors and memory is becoming as consequential as arithmetic throughput, particularly in inference systems serving long-context and low-batch workloads.

PIM places computation within, or immediately beside, the memory array. That changes the limiting resource from external memory traffic to local parallelism within memory banks. A Department of Energy survey describes data movement as roughly two orders of magnitude more energy-intensive than computation and documents performance and energy gains from PIM designs across attention, database, HPC, and graph workloads. Commercial memory suppliers have consequently pursued implementations that preserve familiar memory interfaces while adding localized compute. SK hynix reports that its GDDR6-AiM operates at 16 Gbps, cuts data-transfer power by up to 80%, and can raise targeted-workload throughput by up to 16 times. Samsung reported that HBM-PIM delivered more than twice the performance and over 70% lower energy use in its evaluated AI and HPC workloads. ^{[1]U.S. Department of Energy, Office of Scientific and Technical Information, A Survey on the Expanding Scope and Interdisciplinary Opportunities for Processing-in-Memory Techniques, 2024, osti.gov}

The demand context is increasingly power-constrained. Global data-center electricity consumption was 415 TWh in 2024 and is expected to approach 945 TWh by 2030; the IEA identifies accelerated servers as a major source of incremental demand. PIM is not a universal GPU substitute, but it can change the cost curve for memory-bound layers by keeping attention, vector operations, or database predicates close to stored data. ^{[2]International Energy Agency, Energy and AI, 2025, iea.org}

The market's growth thesis therefore rests on a tension. Rising electricity demand makes lower energy per useful inference commercially valuable, yet the architectures most capable of delivering it must prove predictable accuracy, manageable programming, and acceptable memory-density economics. Suppliers that couple memory innovation with usable runtimes and system validation should capture more value than suppliers that present isolated silicon metrics.

Key Drivers

AI and generative AI workloads. Transformer inference repeatedly moves weights and key-value-cache data through the memory hierarchy, which makes long-context serving disproportionately sensitive to bandwidth and energy. PIM attention accelerators examined in the DOE survey achieved up to 2.81 times higher performance and 2.67 times better energy efficiency than the cited conventional baselines. As accelerated-server electricity use rises, operators have an incentive to evaluate hardware by energy and latency per served token rather than by nominal compute alone.

HBM and advanced memory. HBM is a natural entry point because its bandwidth density already targets AI accelerators. Samsung's HBM-PIM retained HBM2 PHY compatibility in its evaluation, reducing the integration discontinuity for existing accelerator systems. SK hynix's GDDR6-AiM shows an alternative route through graphics-memory-class devices. Their work on LPDDR6 PIM standardization indicates that the opportunity may eventually extend from data centers to power-constrained mobile inference, although standardization should not be confused with volume deployment. ^{[3]Samsung Electronics, Samsung Develops Industry's First High Bandwidth Memory with AI Processing Power, February 2021, news.samsung.com}

CXL memory expansion. Disaggregated memory makes a wider PIM addressable market possible when capacity, rather than raw compute, constrains a workload. The DOE survey identifies CPU-mediated communication as a meaningful limitation in certain DRAM-PIM configurations and reports substantial gains from near-data processing designs using CXL-related interfaces. The commercial implication is not that every CXL device becomes a PIM device; rather, coherent memory expansion can provide a system-level route to attach specialized memory compute without abandoning the host architecture.

Public semiconductor investment. U.S. CHIPS for America funding totals USD 50 billion, including USD 39 billion for manufacturing incentives and USD 11 billion for R&D. The Commerce Department's award to SK hynix includes up to USD 458 million in direct funding and up to USD 500 million in loans for a USD 3.87 billion Indiana investment centered on advanced packaging and HBM-related capability. These programs lower financing and supply-chain risk for advanced-memory capacity, but they do not resolve PIM software readiness; public manufacturing support and application enablement will progress on separate schedules. ^{[4]National Institute of Standards and Technology, CHIPS for America, 2024, nist.gov}

Energy-efficient computing. PIM's potential is most valuable where power availability limits usable AI capacity. The mechanism is specific: local execution avoids a portion of high-energy off-chip data transfers, rather than merely improving conventional compute utilization. The IEA's projected growth in data-center electricity demand makes that attribute relevant to siting and capacity planning as well as device procurement.

Key Restraints

Hardware cost and integration. Adding logic to DRAM can impose a 25–50% density penalty, according to the DOE survey. That trade-off matters because PIM competes not only with GPUs but also with inexpensive conventional memory. The silicon premium is compounded by validation across memory controllers, drivers, thermal design, and serving software. Interface-compatible approaches such as Samsung's HBM-PIM can reduce this burden, but compatibility also constrains how much logic can be added to a memory device. Early adoption will therefore favor workloads where avoided power, latency, or infrastructure spend can be measured against the premium.

Software compatibility. PIM programming requires choices about data placement, bank-level parallelism, kernels, and host-device coordination that conventional GPU users do not routinely manage. The barrier is commercial as much as technical: a hardware advantage that needs bespoke model partitioning can be difficult to deploy in a cloud environment built around standardized serving stacks. Mythic's CAMP SDK supports ONNX, PyTorch, TensorFlow, and TensorRT pathways, demonstrating the value of framework bridges, but such support does not make heterogeneous PIM behavior transparent across all models.

This makes standards and deployment evidence more important than a single device benchmark. Hardware suppliers that preserve familiar interfaces, publish repeatable integration paths, and demonstrate mixed PIM-GPU operation can shorten qualification cycles. Conversely, a device that requires a new programming model without a sharply bounded workload advantage is likely to remain confined to technical pilots despite attractive energy metrics.

Processing-in-Memory (PIM) Market Segment Analysis

By memory technology

DRAM-based PIM leads with USD 420.0M, or 68.7%, of 2025 revenue and is projected to grow at 27.6% CAGR. Its position reflects manufacturing maturity and proximity to existing HBM and GDDR accelerator supply chains. The commercial advantage is qualification: architectures that work with established memory interfaces can enter infrastructure already designed around high-bandwidth memory. Its slower growth than emerging technologies reflects a different constraint, however: logic integration can reduce usable density. ^{[5]SK hynix, SK hynix Develops PIM, Next-Generation AI Accelerator, February 2022, news.skhynix.com}

SRAM-based PIM accounts for USD 91.7M and 15.0% of 2025 revenue, growing at 29.2% CAGR. SRAM favors deterministic, low-latency digital inference. d-Matrix's Corsair platform uses digital in-memory compute and reports 150 TB/s of internal DIMC bandwidth, 2,400 TFLOPs of 8-bit compute, and Llama 3 inference performance figures on PCIe Gen5 hardware. This profile is relevant when token latency and reproducible numerical behavior outrank memory capacity. ^{[6]d-Matrix, d-Matrix Unveils Corsair, the World's Most Efficient AI Computing Platform for Inference in Datacenters, November 2024, d-matrix.ai}

Non-volatile technologies represent the principal growth option. MRAM-based PIM, although only USD 37.6M in 2025, has the highest memory-technology CAGR at 35.4%; ReRAM-based and Flash-based PIM follow at 34.3% and 33.7%. A 40-nm STT-MRAM compute-in-memory macro reported 7.02–112.3 TOPS/W across 4- to 16-bit configurations, 7.4–29.6 ns latency, and matched reported accuracy targets for selected ResNet and physics-informed neural-network tests. Non-volatility can avoid refresh and model-reload overhead, but product outcomes still depend on endurance, precision, and production consistency rather than laboratory efficiency alone.

By computing architecture

Digital PIM is the largest architecture at USD 375.4M and 61.4% share in 2025, with a 30.1% CAGR. It offers deterministic arithmetic and aligns with production inference requirements, including emerging reduced-precision formats. Analog PIM holds USD 168.4M and 27.5% share, growing at 28.4%. Mythic reports 120 TOPS/W and 17 fJ per MAC for its analog architecture. These claims underline analog PIM's energy proposition, while its commercial challenge remains keeping accuracy stable across variation and deployment conditions. Mixed-signal PIM, at USD 67.7M and 11.1% share, trades some analog efficiency for digital control over interfaces and nonlinear operations.

By application and end-user

AI & ML is the largest application at USD 318.0M, or 52.0%, in 2025. HPC and scientific computing (USD 112.9M) and data analytics and database processing (USD 74.8M) offer additional memory-bound workloads; the DOE survey reports PIM gains in climate modeling and OLTP/OLAP tests. Computer vision and NLP, growing at 34.7% and 35.6%, respectively, reward low-power localized inference, particularly where models must remain active at the edge. IT and cloud services lead end-user demand; consumer electronics, automotive, telecommunications, industrial, healthcare, aerospace and defense address different power, latency, and qualification requirements. The absence of end-user market values means vertical comparisons should be read as adoption conditions rather than revenue rankings.

Application growth reinforces this split. NLP and vision expand faster than the aggregate market because they increasingly require inference close to the device or data source. Yet the addressable opportunity is conditional: analog and non-volatile designs must translate energy advantages into repeatable accuracy and manageable developer tooling. The winning architecture will vary by the cost of moving data, the accepted precision range, and whether the customer can qualify a specialized runtime.

Processing-in-Memory (PIM) Market Regional Analysis

North America

North America leads the market with USD 255.0M in 2025, or 41.7% share, and is forecast to reach USD 3,462.8M by 2035 at a 28.9% CAGR. The United States contributes USD 234.0M in 2025, while Canada contributes USD 21.0M. The region combines hyperscale inference demand with a concentration of specialized companies, including EnCharge AI, MemryX, GSI Technology, d-Matrix, and Mythic AI. CHIPS incentives for advanced memory and packaging add a supply-chain dimension to an otherwise demand-led market. ^{[7]U.S. Department of Commerce, Biden-Harris Administration Announces CHIPS Incentives Award with SK hynix to Advance U.S. Technological Leadership and Expand Capacity of Chips Crucial to the AI Supply Chain, December 2024, commerce.gov}

Asia Pacific

Asia Pacific is close behind at USD 241.4M and 39.5% share in 2025, and is projected to become the largest region at USD 3,777.6M by 2035, with a 30.7% CAGR. China grows from USD 72.3M to USD 1,314.6M, South Korea from USD 60.7M to USD 868.9M, Japan from USD 42.0M to USD 521.3M, India from USD 20.2M to USD 491.1M, and Australia from USD 10.0M to USD 113.3M. South Korea is central to the advanced-memory supply side through SK hynix and Samsung. The region also includes Syntiant, PIMIC, TetraMem, Witmem (Zhicun Technology), HOUMO.AI, and Pimchip, creating a broader competitive base across cloud, mobile, and edge use cases.

Europe

Europe represents USD 69.1M in 2025 and is forecast to reach USD 765.7M by 2035 at 26.2% CAGR. Germany rises from USD 19.6M to USD 252.7M, ahead of the UK, France, Italy, and Spain. Industrial AI, automotive, and edge vision provide a different demand mix from North American cloud deployment. Axelera AI is the authorized European competitor, and its edge orientation illustrates the region's potential in application-specific inference rather than volume HBM supply.

Latin America

Latin America grows from USD 23.2M to USD 263.8M at a 26.6% CAGR. The region's PIM uptake is mainly tied to cloud-service availability and AI deployment by enterprises rather than a domestic advanced-memory manufacturing base. Middle East & Africa grows from USD 24.5M to USD 238.2M at a 25.5% CAGR. Saudi Arabia, the UAE, and South Africa are the principal identified markets, rising from USD 6.4M, USD 4.9M, and USD 6.6M in 2025 to USD 77.4M, USD 46.5M, and USD 58.4M, respectively. Demand is likely to follow data-center and public AI-infrastructure investment, making product availability and system-integration capacity decisive.

Europe's route is more application-specific, particularly industrial, automotive, and edge inference. Latin America and the Middle East & Africa are less likely to set memory technology roadmaps, but their growth can be meaningful where new data-center capacity bypasses legacy infrastructure. For PIM suppliers, this means go-to-market models should differ: system co-design and hyperscaler qualification in North America; supply-chain and ecosystem partnerships in Asia Pacific; and workload-focused solutions in Europe and emerging regions.

Processing-in-Memory (PIM) Market Share & Competitive Landscape

SK hynix leads the 2025 market with 29% share, followed by Samsung Electronics at 11%; Syntiant holds 5%, Mythic AI 4%, d-Matrix 4%, and other suppliers collectively 47%. The structure combines memory incumbents able to integrate compute into high-volume memory products with specialists optimized for particular inference conditions.

SK hynix's GDDR6-AiM and AiMX programs position it around heterogeneous data-center inference. Its 2025 AiMX demonstration placed memory-bound attention on AiMX cards and compute-bound projection layers on H100 GPUs in a Supermicro environment using vLLM. Samsung's HBM-PIM differentiates through in-memory AI engines located at HBM banks and compatibility with established HBM2 signaling. Both incumbents are positioned to benefit if PIM enters memory-interface standards, but their central challenge is converting technical compatibility into broad software support. ^{[8]SK hynix, AI Infra Summit 2025: SK hynix Showcases Innovative AiM Solution for Accelerating AI, September 2025, news.skhynix.com}

Syntiant addresses low-power, always-on edge inference. Mythic AI focuses on analog PIM and reports 120 TOPS/W and broad framework interfaces through CAMP. d-Matrix targets data-center inference through Corsair's digital in-memory compute; it reports PCIe Gen5 implementation, 150 TB/s DIMC bandwidth, and an OCP Micro-scaling format focus. EnCharge AI, MemryX, GSI Technology, PIMIC, TetraMem, Witmem, HOUMO.AI, Pimchip, Axelera AI, and XCENA occupy regional, niche, or disruptor positions. Their differentiation will depend on a specific mix of memory substrate, workload specialization, software accessibility, and channel access rather than on a common PIM feature set. ^{[9]Mythic AI, Mythic to Challenge AI's GPU Pantheon with 100x Energy Advantage and Oversubscribed USD 125M Raise, December 2025, mythic.ai}

Recent Industry Developments

In September 2025, SK hynix showed an AiMX-based heterogeneous inference configuration at AI Infra Summit, using four AiMX cards with two H100 GPUs in a Supermicro server and vLLM.

In December 2025, Mythic AI announced a USD 125 million oversubscribed financing led by DCVC, with Honda Motors and Lockheed Martin identified as strategic participants. The company paired the financing announcement with its analog-PIM efficiency and software-platform positioning.