Compute-In-Memory (CIM) Chip Market Size & Share 2026-2035

Compute-In-Memory (CIM) Chip Market Size

The global compute-in-memory (CIM) chip market is valued at USD 500 million in 2025 and is projected to reach USD 687.7 million in 2026 and USD 12.8 billion by 2035, expanding at an approximately 38.4% CAGR during 2026–2035.

CIM places multiply-accumulate operations close to, or within, the memory arrays holding neural-network weights. The architecture targets the data-movement burden that constrains inference throughput and power efficiency in conventional processor-memory designs.

CIM is moving from a circuit-design proposition toward a product-qualification challenge. IBM's NorthPole research architecture integrated 192 MB of SRAM across a 256-core design, illustrating how distributed on-chip memory can reduce reliance on off-chip weight movement for neural inference . The commercial opportunity is strongest where inference workloads are sustained enough for lower energy per operation and lower latency to affect system procurement, including cloud inference clusters, automotive and industrial edge systems, and battery-constrained embedded devices. ^{[1]IBM Research, Analog AI: In-Memory Computing for Energy-Efficient Deep Learning, research.ibm.com. (research.ibm.com)}

The supply chain combines advanced memory design, logic-node access, mixed-signal or digital design expertise, compiler support, packaging, and systems integration. This makes CIM adoption more complex than substituting one accelerator card for another. Memory manufacturers can adapt established DRAM, SRAM, or Flash roadmaps into processing-in-memory products, while fabless vendors must secure foundry capacity and prove that their software stack supports deployment, model conversion, monitoring, and lifecycle management. The ability to integrate CIM arrays with standard interfaces and established server or edge-device architectures will therefore shape design-win conversion more than theoretical compute efficiency alone.

The investment case is not based on a universal replacement of GPUs or CPUs. CIM is most compelling when models repeatedly move large weight sets, when energy availability limits throughput, or when latency and power envelopes rule out conventional accelerators. IBM's demonstrated efficiency advantage for NorthPole on a comparable process node supports the technical premise, but broad market conversion still depends on software portability, reliability validation, and integration economics . The projected expansion to USD 12.81 billion by 2035 therefore assumes that vendors translate memory-centric efficiency into qualified products rather than relying solely on benchmark performance. ^{[2]Wiley, All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices, doi.org. (doi.org)}

Key Drivers

AI inference is increasingly limited by data movement rather than arithmetic throughput. During autoregressive large-language-model inference, model weights must be repeatedly accessed for every generated token. This makes memory access a material determinant of latency, accelerator utilization, and energy draw . A CIM-integrated TPU research design reported a 44.2% performance improvement for generative-model inference and a 27.3× reduction in matrix-multiply-unit energy consumption relative to its cited baseline TPUv4i configuration . Such results matter commercially because cloud operators purchase usable throughput and cost per inference, not peak operations per second. ^{[3]Bowen, Patrick, et al., Analog, In-Memory Compute Architectures for Artificial Intelligence, arXiv, arxiv.org. (arxiv.org)}

Electricity availability has become an infrastructure constraint for AI deployment. U.S. data centers consumed 176 TWh in 2023, equivalent to 4.4% of national electricity consumption, according to Lawrence Berkeley National Laboratory . As AI server deployment rises, power delivery, cooling, and grid interconnection can delay capacity additions even where capital is available. CIM can improve the economic case for inference expansion by reducing transfers between memory and compute, though the realized benefit depends on workload characteristics, precision targets, and surrounding system overhead. ^{[4]Lawrence Berkeley National Laboratory, In-Memory Computing and Energy-Efficient AI Hardware Research, eta-publications.lbl.gov.}

Edge deployments widen the addressable market beyond hyperscale infrastructure. Automotive perception, industrial inspection, cameras, wearables, and connected sensors require local inference where cloud round trips create latency, bandwidth, privacy, or resilience drawbacks. Flash- and SRAM-based CIM are particularly relevant because they can retain model weights locally while reducing off-chip memory transactions. Rain AI began shipping demonstration hardware for low-power analog neuromorphic computing in October 2024, signaling the transition of specialized edge-CIM approaches toward customer evaluation .

Conventional architectures face a memory-wall problem that cannot be addressed solely through higher compute density. High-bandwidth memory improves data supply to GPUs, but it does not remove the energy and latency cost of moving data between separate storage and processing domains. CIM changes this physical relationship by executing selected operations where the data reside. The approach is especially relevant to matrix-vector and matrix-matrix operations used in neural inference, although it is not equally suitable for all model operators or precision requirements .

Memory technology progress is broadening the set of commercially viable CIM substrates. Samsung has reported throughput and energy improvements from HBM-PIM, LPDDR5-PIM, and CXL-based processing-near-memory configurations for LLM-related workloads . SK hynix has separately demonstrated its AiM approach for AI workloads . These programs matter because standardized memory interfaces and proven manufacturing routes can reduce the adoption risk that confronts entirely new accelerator architectures. In parallel, memristive CIM research continues to show the potential for very low-power edge inference, while also illustrating the calibration and reliability work required before large-scale deployment .

Key Restraints

CIM architecture design remains a systems-level engineering problem. Digital implementations must balance SRAM density, precision, routing, and power delivery. Analog implementations add device variation, thermal drift, analog-to-digital conversion, calibration, and model-aware error management. SRAM-CIM reviews emphasize that array architecture and peripheral circuits materially influence accuracy, density, and energy performance, preventing a single macro design from being transferred unchanged across process nodes or applications . The resulting verification burden raises capital requirements and lengthens the time between prototype silicon and customer qualification.

The absence of broadly adopted interfaces and software targets adds a second friction point. Memory manufacturers are making progress on processing-in-memory standardization, but the CIM market includes SRAM, DRAM, Flash, resistive-memory, analog, digital, and hybrid approaches with different programming and deployment requirements . Customers therefore face a portability risk: a model optimized for one architecture may require material recompilation, quantization, or operator redesign for another. This favors suppliers that pair hardware with maintained compiler tools, model libraries, and integration support.

Analog accuracy and endurance constraints limit near-term use cases. Flash and resistive-memory CIM designs can achieve compelling density and energy characteristics, but physical device variation, retention effects, and accumulated analog error complicate high-precision inference. An embedded NAND Flash CIM study identifies threshold-voltage variation and array-level non-idealities as factors that must be addressed to preserve model accuracy . For automotive, healthcare, and industrial applications, qualification requirements can shift the product decision toward digital or hybrid architectures even when analog solutions offer a lower nominal energy-per-operation figure.

Policy requirements also affect commercialization choices. U.S. CHIPS Act guardrails place constraints on certain transactions involving recipients of federal incentives, while export controls can narrow accessible end markets for high-performance AI hardware . In Europe, the risk-based obligations under the EU AI Act increase the importance of traceability and conformity assessment for high-risk applications . These measures do not regulate CIM as a distinct architecture, but they influence where suppliers can sell, how systems are validated, and which reliability characteristics buyers prioritize.

The immediate competitive divide will be between vendors that can commercialize a dependable platform and vendors that can only demonstrate a high-efficiency macro. JEDEC-related processing-in-memory work, memory-vendor product development, and the use of standard host interfaces can reduce buyer risk over time , . Until interoperability and software maturity improve, procurement will favor implementations that demonstrate deterministic performance, integration support, and credible lifecycle management. Analog CIM retains a strong long-term position in constrained edge workloads, but its adoption will be sequenced behind validation rather than determined by energy efficiency alone.

Compute-In-Memory (CIM) Chip Market Segment Analysis

By Memory Technology Type

SRAM-based CIM is the largest memory technology segment, valued at USD 203.22 million in 2025 and projected to reach USD 5.41 billion by 2035, representing an approximately 38.95% CAGR. Its lead reflects manufacturing familiarity: SRAM macros can be integrated with logic using established CMOS flows, allowing designers to pursue high-bandwidth, low-latency inference without relying on emerging nonvolatile-memory behavior. IBM's NorthPole architecture demonstrates the strategic value of this approach by combining distributed SRAM with a dense compute array to reduce off-chip memory dependency .

SRAM's drawback is area cost. Six-transistor cells consume substantially more die area per stored bit than DRAM or Flash, so SRAM-CIM is most economically attractive where low latency and predictable performance justify a higher silicon bill of materials. This aligns the segment with premium cloud inference, networking, industrial vision, and higher-performance edge systems. Its market leadership does not imply that SRAM is the universal CIM substrate; it indicates that established manufacturing and deterministic behavior remain especially valuable during the market's initial commercial phase.

Flash-based CIM is forecast to be the fastest-growing memory technology type, increasing from USD 166.13 million in 2025 to USD 4.67 billion in 2035 at an approximately 39.71% CAGR. Its nonvolatile storage allows neural weights to remain on-chip when power is interrupted, a useful characteristic in embedded devices that require immediate local inference. IEEE research on computing in or near Flash identifies distinct roles for 3D NOR and 3D NAND approaches in high-bandwidth digital computing, search, and analog multiply-accumulate operations .

The commercial value of Flash-CIM is strongest where designers must jointly manage energy, memory capacity, and standby behavior. This includes sensor nodes, cameras, wearables, and selected automotive functions. However, Flash-CIM suppliers must demonstrate that endurance, threshold-voltage control, inference accuracy, and tool support meet product-specific requirements. The fast growth forecast therefore reflects expanding edge demand and a favorable cost-per-bit profile, not the elimination of engineering trade-offs.

DRAM-based CIM is valued at USD 78.54 million in 2025 and is expected to reach USD 1.92 billion by 2035, growing at an approximately 37.76% CAGR. This segment is centered on processing-in-memory and processing-near-memory approaches that retain the capacity advantages of DRAM while adding compute capability close to high-bandwidth data stores. Samsung's HBM-PIM and LPDDR5-PIM work, together with SK hynix's AiM development, position DRAM-CIM primarily in high-throughput data center and memory-centric AI applications , . ^{[5]IBM Research, In-Memory Computing: Non-Von Neumann Architectures for AI, doi.org.}

Other substrates, including RRAM, PCM, MRAM, and FeFET-based CIM, account for USD 52.11 million in 2025 and are projected to reach USD 794.39 million in 2035. These technologies offer valuable nonvolatility or analog-computing potential but remain constrained by yield, endurance, retention, and integration challenges. Their lower approximately 31.21% CAGR reflects a commercialization path that is likely to remain selective until manufacturing consistency and qualification evidence improve.

By Architecture Type

Digital CIM is the largest architecture segment, contributing USD 217.53 million in 2025 and expected to reach USD 5.74 billion by 2035 at an approximately 38.81% CAGR. Digital implementations preserve discrete computation and are generally better suited to applications that require deterministic outputs, familiar quantized model formats, and clearer verification paths. This makes them commercially relevant for cloud inference and regulated edge applications where predictable behavior can outweigh the maximum possible efficiency benefit.

d-Matrix's Corsair platform illustrates the digital-CIM proposition for generative AI inference: its architecture embeds processing elements in memory arrays to reduce data movement, while its commercial positioning focuses on data center deployment rather than a standalone circuit metric . Digital designs still require specialized compilers and memory-aware execution models, but they can reduce the qualification burden associated with analog variation.

Analog CIM is the fastest-growing architecture type, rising from USD 155.72 million in 2025 to USD 4.38 billion in 2035 at an approximately 39.70% CAGR. It performs computation using physical properties such as current, charge, or conductance, potentially delivering superior area and energy efficiency for medium-precision inference. Research on analog SRAM-CIM accelerators demonstrates the architecture's potential for high energy efficiency, while also showing the need for calibration and system-level accuracy management .

The growth premium reflects the importance of energy per inference in client devices and embedded systems. EnCharge AI's February 2025 financing round supports continued commercialization of analog in-memory computing for client platforms . The segment's outlook depends on whether suppliers can convert laboratory-level performance into repeatable silicon behavior, robust software workflows, and customer-acceptable accuracy.

Hybrid CIM represents the practical middle ground, generating USD 126.74 million in 2025 and projected to reach USD 2.69 billion by 2035 at an approximately 35.79% CAGR. By combining analog compute blocks with digital correction or control circuitry, hybrid designs can retain some efficiency advantages while addressing precision and reliability concerns. Their slower forecast growth relative to pure analog systems reflects additional architectural complexity, but the approach may be attractive where a full analog design cannot meet application-specific validation thresholds.

By Application

Data Center & Cloud AI is the largest application segment, valued at USD 162.25 million in 2025 and forecast to reach USD 4.30 billion by 2035 at an approximately 38.88% CAGR. The segment captures high-value systems where energy use, memory bandwidth, and inference latency have direct operating-cost implications. Cerebras's CS-3, built around the WSE-3 wafer-scale engine, is an example of a system designed to concentrate compute and on-chip memory for AI workloads . The scale and utilization of cloud deployments allow efficiency gains to compound across large serving fleets.

Groq's LPU-based inference offering represents a different commercial route: deterministic inference hardware can be monetized through cloud API access rather than only through direct hardware sales . These business models shift buyer evaluation toward tokens per dollar, available capacity, latency, and service reliability. CIM suppliers addressing this segment need more than chip performance; they require software integration, customer support, data center deployment expertise, and a credible path to scale.

Edge AI is the fastest-growing application segment, expanding from USD 121.49 million in 2025 to USD 3.42 billion in 2035 at an approximately 39.71% CAGR. Edge deployments reward architectures that reduce memory traffic because power consumption, battery capacity, thermal design, and response time are tightly linked. Automotive perception, industrial vision, and smart-camera applications can create particularly attractive opportunities, but only where the solution meets safety, reliability, and long-life requirements.

IoT & Embedded applications account for USD 88.54 million in 2025 and are projected to reach USD 2.17 billion by 2035. Low-power local inference and nonvolatile weight storage favor Flash- and emerging-memory CIM solutions, but unit economics are more volume-sensitive than in data centers. Vendors must demonstrate that the energy benefit exceeds the added cost and integration effort relative to microcontrollers, NPUs, or cloud-assisted architectures.

HPC & Industrial Automation contributes USD 72.31 million in 2025 and is projected to reach USD 1.69 billion by 2035. Buyers in this segment value deterministic response, uptime, integration with existing control systems, and long-term availability. Others, including government, defense, smart-city, and early medical-imaging deployments, account for USD 55.41 million in 2025 and are forecast to reach USD 1.21 billion by 2035. These applications can support early qualification programs but often require longer procurement cycles and stringent validation.

By End-User Industry

IT & Telecom is the principal end-user industry in 2025, encompassing cloud operators, enterprise AI infrastructure, and telecom-network workloads. The sector is positioned to adopt CIM where operators can validate lower energy use and higher effective memory bandwidth at production scale.

Automotive is strategically important because ADAS and in-vehicle AI require local processing under fixed thermal and power conditions. The segment will favor architectures that can meet functional-safety and reliability requirements, making digital and hybrid CIM particularly relevant during early deployment. Consumer electronics offers volume potential for low-power analog and Flash-CIM systems, while healthcare adoption will depend on device validation, traceability, and patient-data handling requirements. Industrial users prioritize deterministic behavior and long lifecycle support, which may slow adoption but create durable opportunities for suppliers that clear qualification barriers.

The technology mix follows the same two-speed pattern. SRAM and digital CIM lead because they reduce qualification and software risks for performance-sensitive deployments. Flash and analog CIM grow faster because nonvolatile storage and lower energy per inference better match intermittent-power and thermally constrained devices. Suppliers that position these architectures as substitutes will miss the commercial reality: the more durable opportunity is to match substrate and architecture choices to the accuracy, power, lifetime, and integration constraints of each deployment class.

Compute-In-Memory (CIM) Chip Market Regional Analysis

North America

North America is valued at USD 157.08 million in 2025 and is expected to reach USD 3.84 billion by 2035, advancing at an approximately 37.76% CAGR. The United States anchors regional demand through hyperscale AI infrastructure, advanced chip design activity, and a concentration of CIM-oriented companies including Cerebras, Groq, d-Matrix, EnCharge AI, Mythic, Lightmatter, IBM, and Micron. Canada contributes through engineering and AI hardware activity, including Toronto-based Untether AI and d-Matrix operations.

U.S. policy strengthens the regional design and manufacturing ecosystem. The CHIPS and Science Act authorized major semiconductor incentives and associated guardrails, shaping both domestic supply-chain decisions and commercial partnerships . North American suppliers benefit from sophisticated cloud and enterprise buyers, but export controls and customer concentration can constrain global scale. Success in the region will depend on converting technical differentiation into production deployments with sufficient software support and operational reliability. ^{[6]The Conference Board, Artificial Intelligence Computing Infrastructure and Energy Demand, conference-board.org.}

Europe

Europe accounts for USD 87.78 million in 2025 and is projected to reach USD 1.92 billion by 2035, at an approximately 36.24% CAGR. Germany, the United Kingdom, France, Spain, Italy, Russia, and the rest of Europe contribute through automotive, industrial, research, and enterprise AI demand. The European Chips Act entered into force in September 2023 and established a framework intended to strengthen semiconductor capacity and resilience .

Europe's opportunity is more concentrated in qualified industrial and regulated deployments than in hyperscale accelerator volume. The EU AI Act's risk-based framework makes traceability and validation increasingly relevant for hardware used in high-risk AI systems . The European Court of Auditors has also highlighted execution risk in the region's semiconductor strategy, noting that stated manufacturing ambitions face practical implementation challenges . Accordingly, European CIM adoption is likely to reward suppliers that combine technical performance with compliance documentation, automotive qualification, and local integration capability.

SoftBank's acquisition of Graphcore in July 2024 illustrates the difficulty of scaling independent European AI processor vendors against entrenched GPU ecosystems . Graphcore's IPU approach, which tightly couples substantial on-chip memory with compute, remains relevant to the broader memory-centric computing direction, but the transaction demonstrates that architecture quality alone does not secure commercial scale.

Asia Pacific

Asia Pacific is both the largest and fastest-growing regional market, increasing from USD 201.90 million in 2025 to USD 6.02 billion by 2035 at an approximately 40.52% CAGR. Its position rests on the concentration of memory manufacturing, semiconductor investment, domestic AI demand, and regional design talent. China, India, Japan, South Korea, Australia, and the rest of Asia Pacific contribute different capabilities across manufacturing, memory technology, embedded electronics, sovereign AI infrastructure, and automotive demand.

South Korea provides the region's strongest commercial memory-CIM foundation through Samsung and SK hynix. Their processing-in-memory programs connect CIM development to established DRAM, HBM, and mobile-memory ecosystems , . China adds a large domestic research and patent base, alongside state-backed semiconductor investment. Patent activity involving Hangzhou Zhicun Technology, also known as WitMem, demonstrates continued development of multi-chip in-memory processing configurations . ^{[7]ServeTheHome, In-Memory Computing and Emerging AI Accelerator Technologies, servethehome.com.}

Japan is strengthening its advanced semiconductor and AI technology support. Japan's Ministry of Economy, Trade and Industry advanced legislative measures in February 2025 to support semiconductor and AI-related technology investment . India's IndiaAI Mission and semiconductor policy efforts broaden the region's prospective demand base for sovereign AI, mobile devices, automotive electronics, and local chip design . Regional growth will be influenced by export-control exposure, advanced-node and HBM access, and the ability of local vendors to integrate hardware with viable software ecosystems.

Latin America

Latin America is valued at USD 25.93 million in 2025 and is projected to reach USD 461.26 million by 2035, representing an approximately 33.44% CAGR. Brazil leads regional demand through its digital economy, cloud expansion, and public-sector technology initiatives. Mexico's electronics manufacturing base and proximity to North American automotive supply chains create a narrower but relevant opportunity for edge and embedded CIM adoption.

The region's growth profile is shaped by cost sensitivity and lower near-term AI infrastructure intensity than North America or Asia Pacific. Buyers are likely to prioritize total cost of ownership, local support, and integration with hybrid cloud-edge systems. This favors solutions with clear power, latency, or device-cost advantages rather than premium architectures that require extensive ecosystem investment.

Middle East & Africa

The Middle East and Africa market is valued at USD 27.32 million in 2025 and is forecast to reach USD 563.76 million by 2035, expanding at an approximately 35.15% CAGR. Saudi Arabia and the UAE are the primary regional demand centers, supported by sovereign AI programs and data center development. Groq's 2025 financing and regional infrastructure commitments reflect the role of sovereign buyers in building inference capacity .

Saudi Arabia, the UAE, South Africa, and the rest of MEA present different adoption conditions. Gulf markets can support concentrated, high-value compute procurement, while broader African demand is more likely to emerge through telecommunications, public digital services, and mobile AI applications. Logistics, local systems integration, currency exposure, and availability of skilled deployment partners will influence the pace at which specialized CIM hardware converts from pilot programs to operating infrastructure.

North America will remain commercially influential because it combines specialist chip vendors with hyperscale inference procurement. Europe's trajectory is likely to be more qualification-led, particularly in automotive, industrial, and regulated applications. Latin America and MEA offer selective demand pockets rather than broad early adoption. For suppliers, regional strategy should therefore distinguish between markets that can validate high-performance systems at scale and markets where localized edge economics, sovereign procurement, or compliance requirements determine the first viable design wins.

Compute-In-Memory (CIM) Chip Market Share & Competitive Landscape

The CIM chip market is fragmented because suppliers approach the memory-compute challenge from different starting points: wafer-scale systems, memory products, cloud inference processors, analog edge accelerators, photonic interconnects, and near-memory architectures. Cerebras Systems holds an estimated 18.2% market share in 2025, followed by Samsung Electronics at approximately 12.2%, SK hynix at 8.1%, Intel at 7.9%, and Groq at 6.8%. Other suppliers, including Mythic, d-Matrix, EnCharge AI, Rain AI, Lightmatter, IBM, Micron, Untether AI, and Graphcore, account for an estimated 46.8%.

Cerebras Systems leads through wafer-scale AI systems built around its WSE architecture. The CS-3 system incorporates the WSE-3, which Cerebras states contains 4 trillion transistors and 40 GB of on-chip SRAM . Its competitive advantage is system-scale integration and low-latency inference potential; its exposure is the capital intensity of scaling systems, customer concentration, and the need to sustain a software environment that competes with established GPU platforms.

Samsung Electronics brings vertical integration across memory, foundry services, and system semiconductors. Its HBM-PIM, LPDDR5-PIM, and processing-near-memory work provides an established route to integrate compute functions with high-volume memory technologies . Samsung's primary advantage is the ability to align architecture development with manufacturing and memory roadmaps. Its commercial challenge is to turn technical demonstrations and standards activity into interoperable products adopted by system OEMs and cloud customers.

SK hynix competes through AiM, HBM, and mobile-memory capabilities. Its GDDR6-AiM and AiMX-xPU programs indicate a focus on placing compute close to memory for AI workloads . As a leading HBM supplier, SK hynix also participates in the conventional AI memory value chain that CIM seeks to reshape. This dual exposure provides market insight and manufacturing scale but requires the company to manage product positioning across both conventional high-bandwidth memory and in-memory computing.

Intel participates through AI accelerators, CXL-enabled memory ecosystems, and near-memory computing pathways. Gaudi 3 combines high-bandwidth memory with specialized AI compute and reflects Intel's effort to offer alternatives in enterprise generative AI infrastructure . Intel's CXL involvement can support more standardized approaches to attaching intelligent memory or near-memory devices, although it does not by itself resolve the architectural and software differences across CIM implementations.

Groq has positioned its LPU architecture around deterministic inference execution and high token throughput. Its August 2024 financing round underscored investor interest in alternative AI inference hardware . Groq's competitive model extends beyond chip sales through cloud-based inference access, allowing customers to evaluate performance through service metrics such as response time, throughput, and availability. This model can accelerate customer access but also raises the operational demands of building and maintaining inference infrastructure.

Specialist challengers are pursuing more focused opportunities. d-Matrix addresses data center inference through digital in-memory compute and raised USD 275 million in November 2025 to support commercial scale-up . EnCharge AI targets client and embedded computing with analog in-memory technology . Mythic combines embedded Flash with analog compute and announced a USD 125 million financing round in December 2025 . Rain AI is pursuing low-power analog neuromorphic approaches for edge deployment . These vendors can benefit from targeted product-market fit, but they must overcome the same qualification, foundry access, and software ecosystem barriers that protect larger incumbents. ^{[8]Rain AI, Digital In-Memory Compute for AI Training and Inference, rain.ai. (rain.ai)}

Interconnect and packaging suppliers are increasingly important to scalable CIM deployment. Lightmatter's Passage M1000, announced in March 2025, offers a photonic interconnect platform with up to 114 Tbps of optical bandwidth . The technology does not constitute CIM processing itself, but it can address the cluster-level communication constraints that emerge when multiple memory-centric accelerators are deployed together. Its partnership with Amkor Technology to develop a large 3D photonics package further illustrates how advanced packaging is becoming part of the competitive architecture stack .

Patent activity adds a strategic layer to competition. WIPO reported 3.7 million global patent applications in 2024, with computer technology accounting for 13.2% of filings . In CIM, differentiated IP can cover memory-cell structures, analog calibration, dataflow, compiler methods, packaging, and system integration. Suppliers with defensible patents and demonstrable manufacturing know-how will be better positioned to secure licensing revenue, foundry partnerships, and long-duration customer programs.

Recent Industry Developments

• February 2025 - EnCharge AI closed an oversubscribed Series B financing round of more than USD 100 million. The financing was directed toward commercializing analog in-memory computing solutions for client computing applications .
• March 2025 - Lightmatter introduced the Passage M1000 photonic interposer. The platform provides up to 114 Tbps of optical bandwidth for large AI systems, addressing interconnect requirements that can limit multi-accelerator scaling .
• November 2025 - d-Matrix raised USD 275 million in Series C financing. The company stated that the funding would support commercialization of its digital in-memory compute platform for AI inference .
• December 2025 - Mythic announced a USD 125 million funding round. The financing supports continued development of its Flash-based analog CIM architecture and associated software ecosystem .