Compute Express Link (CXL) Component Market Size & Share 2026-2035

Compute Express Link (CXL) Component Market Size

The global Compute Express Link (CXL) component market was valued at USD 710.1 million in 2025 and is projected to reach USD 891.1 million in 2026 and USD 7.9 billion by 2035, expanding at a 27.53% CAGR during 2026–2035.

CXL shifts server-memory procurement from a node-by-node capacity decision toward a fabric-level utilization decision. Its coherent protocol permits processors, accelerators, and memory devices to exchange data over the PCIe physical layer, while CXL 2.0 introduced the switching and memory-pooling functions that make multi-host resource allocation possible ^{[1]Compute Express Link Consortium, Compute Express Link 2.0 Specification: Memory Pooling, computeexpresslink.org}. CXL 3.0 subsequently added multi-level switching, peer-to-peer access, and fabric-attached memory, extending the architecture from memory expansion within a server toward composable rack-scale infrastructure.

The commercial case is now being tested in production rather than only in benchmark environments. Microsoft Azure reported that 35–44% of DRAM could be assigned to CXL pools while meeting service-level objectives in its evaluated production environment ^{[2]Microsoft Research, Pond: CXL-Based Memory Pooling Systems for Cloud Platforms, microsoft.com}. Meta's Vistara deployment provides a separate operating proof point: its production implementation combines local DDR5 with CXL-attached memory to address workloads constrained by memory capacity rather than compute availability ^{[3]Meta Platforms, CXL-Based Memory and Compute Infrastructure Research, jovans2.github.io}. These deployments make the component opportunity broader than Type 3 memory devices alone. Controllers, switches, retimers, NICs, firmware, and silicon IP become necessary as deployments progress from capacity expansion to pooled-memory fabrics.

CXL 4.0, released in November 2025, moves the roadmap to 128 GT/s over the PCIe 7.0 physical layer and adds bundled-port capabilities and enhanced reliability, availability, and serviceability features. That roadmap expands the design burden for suppliers, particularly in signal integrity, verification, power management, and fabric orchestration. It also preserves a near-term market led by CXL 2.0 memory expansion, since broad availability of PCIe 7.0 host platforms will lag the specification release.

The implication differs by buyer. Hyperscalers can justify custom ASICs, fleet-wide software changes, and reuse of memory recovered from retired servers. Most enterprises will initially purchase merchant controllers and add-in memory devices because their practical objective is capacity relief without a fabric redesign. Suppliers that can convert CXL pooling into a validated, manageable server configuration should gain earlier volume than vendors whose offerings require customers to assemble a full disaggregated architecture.

Key Drivers

AI inference and high-memory compute workloads

AI inference increasingly exposes a mismatch between accelerator compute throughput and the capacity available for model parameters, embedding tables, and KV caches. CXL creates an intermediate memory tier that is more tightly coupled to the processor than network-attached memory. Meta's production results show the commercial relevance of that distinction: Vistara improved average query processing time by 29% for CacheB and increased sustainable queries per second per server by 33% for CacheA. The component demand consequence is direct: memory-capacity pressure raises demand first for controllers and expanders, then for switches and retimers as pools move beyond individual servers.

Alibaba's Beluga work further indicates that CXL-based pooling can improve time-to-first-token and query throughput relative to RDMA-based disaggregation in AI-serving workloads ^{[4]Alibaba Group, CXL-Based Memory Systems and Resource Management for Cloud Computing, arxiv.org}. Such evidence does not mean every model-serving workload will benefit equally. It does indicate that CXL components are becoming part of the infrastructure decision for workloads where memory movement, rather than GPU arithmetic, constrains service economics.

Memory pooling and DRAM-utilization economics

Pooling addresses the cost of buying memory for each server's peak requirement while leaving capacity unused across the fleet. Microsoft's production-cluster analysis found 3–27% DRAM stranding and reported that approximately half of evaluated virtual machines used less than half of their rented memory. CXL pooling can convert part of that stranded capacity into a shared resource, provided the workload's latency sensitivity and the fabric-management overhead remain acceptable.

The savings mechanism is stronger where DRAM represents a large share of server cost. The Open Compute Project's end-user analysis, incorporating operator perspectives from Meta, Microsoft, and Uber, identified DRAM as approximately half of server cost in the relevant context and cited average non-peak memory utilization near 60% for Uber ^{[5]Open Compute Project, Compute Express Link (CXL) and Open Hardware Infrastructure, opencompute.org}. This makes memory expansion and pooling particularly relevant to distributed caches, analytics clusters, in-memory databases, and inference systems with variable memory footprints.

Composable infrastructure and rack-scale deployment

CXL 3.x broadens the addressable component stack by supporting multi-level switching and fabric-attached memory. The architecture requires more than an expander: it raises requirements for switch fabrics, retimers, NIC connectivity, platform firmware, and policy software. Marvell's Structera S 30260, announced for sampling in 2026, illustrates the move toward merchant silicon for this use case, with 260 lanes and up to 4 TB/s of aggregate bandwidth ^{[6]Marvell Technology, CXL Near-Memory Compute and Expansion Solutions, marvell.com}.

The transition will not be linear. Single-host expansion can be adopted during normal server refresh cycles, whereas multi-host fabrics depend on qualified cabling, topology planning, isolation controls, and software capable of assigning pooled memory predictably. This sequencing favors controllers and add-in memory devices in the early commercial phase, followed by higher growth in switching and connectivity components as fabric deployments scale.

Energy efficiency and server-count reduction

CXL can improve workload-level energy economics when pooling reduces the number of lightly utilized servers required to satisfy memory-capacity peaks. Meta reported a 30% compute-capacity reduction for its Cosco big-data and shuffle service and 15% fewer servers for its CI/CD build fleet. These outcomes arise from improved capacity utilization, not from a universal reduction in the energy consumed by every memory access.

Hardware compression can further change the economics of CXL-attached memory. ZeroPoint and Seagate demonstrated inline compression in a CXL memory tier at the 2025 OCP Global Summit, reporting up to 2.25× compression with less than 1% CXL traffic overhead ^{[7]ZeroPoint Technologies, ZeroPoint Technologies Announces ZeroStream for AI and Data Center Memory Optimization, prnewswire.com}. For component suppliers, compression shifts value toward controller and IP differentiation because usable capacity can increase without proportionally increasing DRAM devices or chassis footprint.

Standards and ecosystem expansion

CXL's use of the PCIe physical layer lowers adoption risk for server and semiconductor vendors already investing in PCIe roadmaps. The CXL Consortium's roadmap from CXL 2.0 through CXL 4.0 creates a common interface for host processors, memory modules, switches, retimers, and IP providers. This interoperability is commercially important because component vendors can address several platform OEMs rather than develop a proprietary interconnect for each deployment.

Silicon IP availability also shortens the path from a specification release to product design. Synopsys announced a CXL 4.0 IP offering incorporating controller, security, PHY, and verification capabilities ^{[8]Synopsys, Compute Express Link (CXL) IP Solutions, synopsys.com}, while Rambus and Alphawave Semi offer CXL controller IP aimed at custom SoC and chiplet designs. The supplier base thus extends beyond memory-module vendors to the design ecosystem that enables CXL integration in accelerators, storage controllers, and networking silicon.

Key Restraints

Restraint Impact Table

Integration cost and performance trade-offs

CXL deployment requires a host platform with native support, compatible memory or fabric devices, firmware qualification, and operating-system policies that understand the distance between local and CXL-attached memory. These requirements create an adoption hurdle for operators that cannot align CXL deployment with a server refresh. The cost is not limited to component procurement; it includes validation of workload placement, NUMA behavior, fault handling, and security isolation.

The performance boundary remains material. Microsoft's Pond research emphasizes that pooled memory must be sized and placed around latency and bandwidth requirements rather than treated as a direct replacement for local DRAM. Meta's Vistara configuration similarly combines 768 GB of local DDR5-6400 with 256 GB of CXL-attached DDR4-2400, showing that deployed systems retain a tiered-memory design rather than moving all memory into a CXL pool. Components are therefore selected according to the workload's hot-data profile, not simply its total memory requirement.

Software and fabric-management maturity

Memory pooling delivers savings only when allocation software can identify which pages, services, or tenants can tolerate access to the CXL tier. CXL 2.0 requires management of partitioned devices and host assignments, while CXL 3.x adds the challenge of coordinating multi-host fabrics. Azure's experience demonstrates that material DRAM allocation to pools is achievable, but it also shows why large operators with platform engineering resources are earlier adopters.

This constraint may slow broad enterprise adoption even while hyperscaler demand accelerates. A server buyer can install a memory expander with relatively limited operational change; a multi-host CXL fabric requires policy controls, observability, failure-domain design, and repeatable qualification. Vendors that package controllers, firmware, hardware reference designs, and lifecycle-management tools can reduce this restraint more effectively than suppliers selling isolated silicon.

The second model is server-refresh-led enterprise adoption. Here, performance tiering and operational complexity remain more important than the theoretical availability of a CXL specification. The market will favor component vendors that make CXL-attached memory behave like an OEM-qualified capacity option, with validated firmware and clear workload-placement guidance. Suppliers that depend on customers to engineer their own fabric will remain exposed to longer qualification cycles.

Compute Express Link (CXL) Component Market Segment Analysis

By Component

Controllers are the largest category, increasing from USD 245.2 million in 2025 to USD 2.45 billion by 2035 at a 26.12% CAGR. They are central to every CXL memory attachment because they connect protocol handling, memory channels, device management, and host interoperability. Their large revenue base reflects demand across both add-in card and integrated-memory architectures.

CXL switches rise from USD 145.5 million in 2025 to USD 1.94 billion by 2035 at a 29.75% CAGR. Their growth exceeds the overall market because switches are needed when pooled memory serves several hosts or when fabrics extend beyond a local server. Marvell's CXL 3.0 switching roadmap illustrates the merchant-silicon response to this phase of demand.

Memory expanders grow from USD 197.9 million in 2025 to USD 1.84 billion by 2035 at a 25.21% CAGR. This category remains the most visible near-term deployment route because it increases usable server memory without waiting for broad fabric adoption. SK hynix completed customer validation of its 96 GB CXL 2.0-based DDR5 module in April 2025, reflecting the shift from development programs to customer qualification ^{[9]SK hynix, SK hynix Advances CXL-Based Memory Solutions for AI and Data Center Applications, prnewswire.com}.

Retimers expand from USD 42.6 million in 2025 to USD 660.5 million by 2035 at a 31.68% CAGR. Higher signaling rates and longer channel paths increase the need for retiming, particularly in dense AI servers, add-in architectures, and rack-scale CXL links. Marvell's Alaska P PCIe Gen 6/CXL 3 retimer family and Montage's 16-lane PCIe 6.x/CXL 3.x retimer address that signal-integrity requirement ^{[10]Montage Technology, Montage Technology Announces Industry-First Trial Production of CXL 3.2 MXC Chip, prnewswire.com}.

Network interface cards are the fastest-growing component category, advancing from USD 41.6 million in 2025 to USD 728.8 million by 2035 at a 33.22% CAGR. Growth reflects the longer-term extension of coherent and memory-sharing architectures into fabric-oriented environments. Others, including bridge devices, PHY IP, power-management components, and associated silicon, increase from USD 37.3 million in 2025 to USD 313.6 million by 2035 at a 23.88% CAGR.

By Form Factor

Add-in cards are the largest form factor, growing from USD 257.9 million in 2025 to USD 2.21 billion by 2035 at a 24.15% CAGR. Their early advantage stems from deployment flexibility: supported servers can add CXL memory capacity through PCIe slots without redesigning the motherboard. This format is suited to first-wave expansion projects where buyers need incremental capacity before committing to pooled-memory fabrics.

Enterprise and datacenter standard form factors grow from USD 229.8 million in 2025 to USD 3 billion by 2035 at a 29.49% CAGR. EDSFF-oriented CXL devices are increasingly relevant to hyperscale designs that prioritize serviceability, standardized density, and rack-level integration. Samsung's CMM-B memory-pooling system, designed around E3.S devices, exemplifies this transition toward standardized serviceable modules.

SoC-integrated solutions are the fastest-growing form factor, rising from USD 168.3 million in 2025 to USD 2.37 billion by 2035 at a 30.46% CAGR. Integrating CXL into CPUs, accelerators, NICs, and custom controllers reduces reliance on discrete interfaces and embeds CXL capability in the server platform. This is commercially consequential because host-side adoption expands the addressable base for downstream CXL devices. Others increase from USD 37.3 million in 2025 to USD 313.6 million by 2035 at a 20.99% CAGR.

By CXL Specification

CXL 1.x remains relevant in installed early-generation systems but has limited pooled-memory functionality. Its role is increasingly transitional because it lacks the switching and multi-host pooling features that drive the larger disaggregation opportunity.

CXL 2.0 is the leading commercial specification through the near term. It supports switching, pooling, and partitioning functions that enable current memory-expansion products and cloud deployments. Astera Labs' Leo controllers supporting Microsoft Azure M-series virtual machines demonstrate the specification's commercial relevance in a public-cloud environment.

CXL 3.x is the fastest-growing specification segment as suppliers position for multi-level switching, fabric-attached memory, and higher-bandwidth PCIe 6.0 links. Samsung and SK hynix have both advanced CXL 3.2 memory roadmaps, while switch and retimer suppliers are extending their products to the fabric-oriented generation.

CXL 4.0 establishes the next design target, with 128 GT/s signaling, bundled ports, and expanded reliability features. Its material revenue contribution will follow availability of compatible host silicon, but its early IP availability affects current semiconductor design decisions.

By Application

AI/ML workloads represent the largest application category because inference and training systems can become memory-capacity constrained before their accelerator compute is fully used. Alibaba's Beluga work demonstrates that CXL-based pooling can improve time-to-first-token and query throughput relative to RDMA-based disaggregation in AI-serving workloads. Meta's production results provide a stronger operational benchmark: CXL-backed disaggregation reduced servers required for ML inference while also improving distributed-cache performance.

Memory pooling and expansion covers in-memory databases, distributed caches, analytics, and other workloads that exceed local DIMM capacity or experience variable memory demand. It is the most immediate adoption path because it can deliver capacity and utilization benefits without requiring a multi-level fabric.

Composable infrastructure remains earlier in its commercial cycle. Its value proposition depends on the ability to allocate compute, accelerators, and memory independently, which elevates demand for switching, retiming, management software, and hardware validation.

In-memory databases and analytics benefit where local DRAM capacity limits dataset size or forces use of more servers. Samsung reported a 32% TPC-DS performance improvement in an SAP HANA configuration using CMM-B and software interleaving. Others includes storage extensions, computational storage, and emerging near-memory processing applications.

By Infrastructure

CSPs and hyperscalers are the leading infrastructure segment because they control sufficiently large fleets to capture savings from reduced DRAM stranding and fewer memory-overprovisioned servers. Meta and Microsoft are publicly documented examples of production CXL development and deployment. Their procurement is likely to pull demand for controllers, memory modules, switches, and software forward of the broader enterprise market.

Neoclouds represent a growing secondary segment. Their AI-centered operating model increases exposure to the KV-cache and memory-capacity bottlenecks addressed by CXL, although they may prefer turnkey products because they generally have less internal platform-engineering capacity than the largest hyperscalers.

Enterprise datacenters are expected to adopt more gradually. Their primary adoption trigger is likely to be a server refresh combined with an OEM-validated memory-expansion product, rather than an immediate move to pooled fabrics. Others includes telecommunications, edge, government, and research-HPC environments.

By End Use

Finance is the largest end-use market, rising from USD 177.5 million in 2025 to USD 1.73 billion by 2035 at a 25.79% CAGR. Risk analytics, transaction processing, fraud models, and in-memory data systems create demand for high-capacity memory configurations. Workloads with the strictest latency requirements will remain dependent on local DRAM, while analytical and capacity-driven tasks are more suitable for CXL tiers.

Telecom advances from USD 152.6 million in 2025 to USD 1.58 billion by 2035 at a 26.58% CAGR, supported by cloud-native network workloads that contend for memory on shared infrastructure. Healthcare is the fastest-growing vertical, increasing from USD 123.2 million to USD 1,714.8 million at a 30.30% CAGR, as genomics, diagnostic AI, and data-intensive clinical computing raise memory requirements.

Oil and gas grows from USD 107.1 million in 2025 to USD 1.25 billion by 2035 at a 28.15% CAGR, reflecting seismic processing and reservoir simulation use cases. Aerospace rises from USD 87.8 million to USD 1.10 billion at a 29.03% CAGR, supported by simulation and high-capacity data-processing requirements. Others increases from USD 61.8 million to USD 547.7 million at a 24.55% CAGR.

The application evidence supports this sequencing. Meta's production system improved CacheB query processing and CacheA sustainable throughput while reducing servers in inference deployments; Alibaba's CXL pooling results similarly point to AI-serving workloads as a demand source for more sophisticated fabrics. SoC integration, forecast to grow at 30.46% CAGR, becomes strategically important because it determines how broadly compatible host platforms become. Suppliers with controller IP, PHY expertise, and validation capabilities will be better positioned than vendors focused solely on discrete memory devices.

Compute Express Link (CXL) Component Market Regional Analysis

North America

North America is the largest regional market, valued at USD 271.1 million in 2025 and projected to reach USD 337.5 million in 2026 and USD 2.79 million by 2035 at a 26.46% CAGR. The region combines hyperscaler demand with a dense supplier base spanning host CPUs, memory technology, connectivity silicon, and IP. The United States is the largest national market, increasing from USD 241.7 million in 2025 to USD 2.46 billion by 2035 at a 26.33% CAGR. Canada grows from USD 29.4 million to USD 326.5 million at a 27.40% CAGR, supported by AI-platform IP activity and cloud infrastructure investment.

North American demand is likely to be weighted toward earlier deployment of pooled memory and CXL-enabled AI infrastructure because Meta and Microsoft have publicly disclosed production-oriented CXL work. This favors suppliers able to meet hyperscaler qualification requirements, including component reliability, firmware support, and scalable platform validation.

Europe

Europe grows from USD 166.2 million in 2025 to USD 1.62 billion by 2035 at a 25.78% CAGR, including USD 205.9 million in 2026. Germany remains the largest specified European market, rising from USD 37.8 million to USD 313.0 million at a 23.70% CAGR. The United Kingdom increases from USD 34.3 million to USD 403.8 million at a 28.12% CAGR, while France, Italy, and Spain reach USD 251.4 million, USD 199.5 million, and USD 149.2 million, respectively, by 2035.

European adoption is shaped by enterprise and sovereign-cloud use cases as well as hyperscaler expansion. The region has relevant IP suppliers, including Alphawave Semi and ZeroPoint Technologies, but the deployment cycle is likely to depend heavily on OEM validation and the availability of manageable, energy-efficient memory-expansion configurations. This makes controllers, IP, and standardized form factors more immediately relevant than full fabric deployments in many enterprise environments.

Asia Pacific

Asia Pacific is the fastest-growing region, expanding from USD 216.6 million in 2025 to USD 278.7 million in 2026 and USD 3.03 billion by 2035 at a 30.39% CAGR. China is the largest regional national market, increasing from USD 85.2 million to USD 1.28 billion at a 31.37% CAGR. India is the fastest-growing specified national market, rising from USD 24.3 million to USD 434.3 million at a 33.55% CAGR.

The region benefits from both demand-side AI infrastructure investment and supply-side concentration of memory and connectivity specialists. South Korea grows from USD 17.8 million to USD 261.2 million at a 30.99% CAGR, reflecting the strategic presence of Samsung and SK hynix. Japan rises from USD 30.4 million to USD 337.1 million at a 27.35% CAGR, while Australia increases from USD 10.8 million to USD 139.7 million at a 29.34% CAGR. CXL adoption in Asia Pacific will not be homogeneous: domestic semiconductor ecosystems, export-control exposure, and varying access to advanced host platforms will shape the product mix by country.

Latin America

Latin America increases from USD 32.3 million in 2025 to USD 39.8 million in 2026 and USD 294.1 million by 2035 at a 24.90% CAGR. CXL demand is tied to the expansion of cloud and colocation capacity rather than an indigenous CXL component-manufacturing base. Brazil and Mexico are the key infrastructure centers; Brazil and Mexico accounted for 82% of new regional data-center capacity in 2025.

The regional opportunity is likely to emerge through hyperscaler and colocation procurement of high-memory server configurations. As a result, near-term demand should concentrate in CXL 2.0 memory expansion and supported server platforms. Larger pooled-memory fabrics will depend on local availability of qualified systems, fabric-management expertise, and sustained AI workload density.

Middle East and Africa

The Middle East and Africa market grows from USD 23.9 million in 2025 to USD 29.3 million in 2026 and USD 206.7 million by 2035 at a 24.23% CAGR. Saudi Arabia rises from USD 7.1 million to USD 64.3 million, the UAE from USD 5.6 million to USD 52.9 million, and South Africa from USD 4.8 million to USD 42.4 million by 2035.

Sovereign AI strategies, cloud-region development, and data-localization priorities create a basis for high-memory infrastructure investment. However, these markets are expected to procure CXL primarily through global OEMs, memory suppliers, and connectivity vendors. Demand will therefore be sensitive to the pace of regional data-center commissioning and the availability of implementation partners capable of supporting CXL-enabled platforms.

North America nevertheless retains a critical role in defining early deployment requirements. Microsoft's demonstrated CXL pooling and Meta's fleet-scale Vistara results establish operating benchmarks for utilization, latency tiering, and server-count reduction. Component suppliers should therefore treat North America as the primary qualification and reference-market center, while positioning Asia Pacific as the largest long-duration volume-growth opportunity. Latin America and MEA offer a different proposition: lower absolute demand, but potential for concentrated orders attached to hyperscaler and sovereign-cloud projects.

Compute Express Link (CXL) Component Market Share & Competitive Landscape

The market combines large processor and memory suppliers with connectivity specialists and IP vendors. Intel holds 14.5% market share, equivalent to USD 103.0 million, followed by Samsung at 13.3% (USD 94.4 million), SK hynix at 10.3% (USD 73.1 million), AMD at 8.6% (USD 61.1 million), and Micron at 7.9% (USD 56.1 million). Marvell holds 4.2% (USD 29.8 million) and Synopsys holds 3.5% (USD 24.9 million). The remaining market is distributed among component, IP, and emerging-specialist suppliers.

Intel shapes the market through CXL-capable Xeon platforms, which determine the host-side compatibility available to memory-expansion suppliers. Intel and Micron demonstrated bandwidth gains using CXL memory expansion modules on Xeon 6 processors, illustrating the importance of host-platform tuning to realized component performance.

Samsung Electronics, SK hynix, and Micron Technology compete through CXL-attached memory modules and their DRAM technology roadmaps. Samsung's CMM-D and CMM-B product strategy targets both device-level expansion and pooled-memory configurations. SK hynix has advanced customer validation and Linux optimization for its CXL memory products. Micron's role is reinforced by its participation in host-platform validation with Intel.

AMD provides an alternative CXL-capable host processor ecosystem, while its CPU and accelerator roadmaps influence the platform base for heterogeneous-memory architectures. Its relevance is amplified by the Vistara deployment's use of an AMD Turin-based memory server configuration.

Marvell, Astera Labs, Credo Technology, and Montage Technology compete in connectivity and controller categories. Marvell spans CXL switches, controllers, and retimers. Astera Labs' Leo controllers support the Microsoft Azure M-series CXL memory deployment. Credo's retimer and active electrical cable portfolio addresses longer-reach PCIe/CXL connectivity, while Montage supplies retimers and memory-extension controllers for AI server and memory-module designs.

Synopsys, Cadence Design Systems, Rambus, Alphawave Semi, and Mobiveil address the CXL IP, controller, verification, and custom-ASIC layer. Their value proposition is tied to the breadth of CXL adoption in host processors, accelerators, NICs, and custom silicon. Synopsys' CXL 4.0 IP offering and Rambus' CXL controller portfolio illustrate the competitive importance of protocol, security, PHY, and verification integration. Alphawave Semi's CXL controller and chiplet-oriented connectivity portfolio address advanced AI and networking designs.

ZeroPoint Technologies competes through memory-compression IP that can increase effective capacity in CXL Type 3 devices, while Wolley represents an emerging MEA-focused participant in composable-memory infrastructure. The competitive field will increasingly be determined by qualification depth, firmware and software integration, power efficiency, and ability to support multiple CXL generations, rather than by controller bandwidth alone.

Recent Industry Developments

November 2025 — CXL Consortium releases CXL 4.0: The CXL Consortium released CXL 4.0, introducing 128 GT/s operation over PCIe 7.0, bundled ports, expanded channel reach, and enhanced memory RAS capabilities.

November 2025 — Astera Labs enables CXL memory expansion on Microsoft Azure M-series VMs: Astera Labs announced that its Leo CXL Smart Memory Controllers supported CXL memory expansion for customer evaluation on Microsoft Azure M-series virtual machines.

October 2025 — ZeroPoint Technologies and Seagate demonstrate inline CXL memory compression: The companies demonstrated CXL memory-tier compression at the OCP Global Summit, reporting up to 2.25× compression with less than 1% CXL traffic overhead.

January 2025 — Montage Technology samples PCIe 6.x/CXL 3.x retimer: Montage began sampling its M88RT61632 16-lane retimer for AI server, active electrical cable, and storage-system applications.

April 2025 — SK hynix completes customer validation of CXL 2.0 DDR5 module: SK hynix announced completion of customer validation for its 96 GB CXL 2.0-based DDR5 module and continued validation work on a 128 GB version.

May 2024 — Marvell launches Alaska P PCIe Gen 6/CXL 3 retimers: Marvell introduced its Alaska P retimer portfolio for accelerated infrastructure, CXL disaggregated memory, and active electrical cable applications.

July 2024 — Marvell introduces Structera CXL products: Marvell launched the Structera family, including memory-expansion controllers and near-memory accelerators for cloud data-center workloads.

June 2026 — Meta discloses Vistara production deployment: Meta presented Vistara at ISCA 2026, describing CXL-based memory disaggregation deployed across millions of servers and reporting up to 25% lower server count for disaggregated ML inference.